1. Rule90（Rule 90）
方法1：
module top_module (output reg [511:0] q,input clk,input load,input [511:0] data
); integer i;always @(posedge clk) beginif (load == 1'b1) beginq <= data;end else beginfor (i=0; i<$bits(q); i=i+1) beginif (i == 0) beginq[0] <= q[1];end else if (i == 511) beginq[511] <= q[510];end else beginq[i] <= q[i+1]^q[i-1];endendendend
endmodule方法2：
根据首位两端的部分计算式：
q[0] = q[1] ^ 1'b0
q[1] = q[2] ^ q[0]
...
q[510] = q[511] ^ q[509]
q[511] = 1'b0 ^ q[510]
可以得出实际用于计算的范围。对于一个n-bit的值q，其计算范围如下所示：
q = { 1'b0, q[n: 1] } ^ { q[n-1: 0], 1'b0 };
对于本题，其计算范围则如下所示：
q = { 1'b0, q[511: 1] } ^ { q[510: 0], 1'b0 };
module top_module (output reg [511:0] q,input clk,input load,input [511:0] data
); always @(posedge clk) beginif (load == 1'b1) beginq <= data;end else beginq <= {1'b0, q[511:1]} ^ {q[510:0], 1'b0};endend
endmodule2. Rule110（Rule 110）
module top_module (output reg [511:0] q,input clk,input load,input [511:0] data
); wire [511:0] q_left, q_right;always @(posedge clk) beginif (load == 1'b1) beginq <= data;end else beginq <= (q_left ^ q_right) | (q_left & q & ~q_right);endendassign q_left = {1'b0, q[511:1]};assign q_right = {q[510:0], 1'b0};
endmodule
)
